1. Field of the Invention
Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to various novel methods of forming punch through stop regions on FinFET devices on CMOS-based integrated circuit (IC) products using doped spacers.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices, i.e., an NMOS device and a PMOS device are opposite type devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
FIG. 1 is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12 that will be referenced so as to explain, at a very high level, some basic features of a traditional FinFET device. In this example, the FinFET device 10 includes three illustrative fins 14, a gate structure 16, a sidewall spacer 18 and a gate cap 20. Trenches 13 are formed in the substrate 12 to define the fins 14. A recessed layer of insulating material 15 is positioned under the gate structure 16 and between the fins 14 in the areas outside of the gate structure, i.e., in the source/drain regions of the device 10. The gate structure 16 is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material or silicon dioxide, and one or more conductive material layers (e.g., metal and/or polysilicon) that serve as the gate electrode for the device 10. The fins 14 have a three-dimensional configuration: a height 14H, a width 14W and an axial length 14L. The axial length 14L corresponds to the direction of current travel, i.e., the gate length (GL) of the device 10 when it is operational. The gate width (GW) direction of the device 10 is also depicted in FIG. 1. As indicated, the gate width direction is transverse to the gate length direction. The portions of the fins 14 covered by the gate structure 16 is the channel region of the FinFET device 10. In a conventional process flow, the portions of the fins 14 that are positioned outside of the spacers 18, i.e., in the source/drain regions of the device 10, may be increased in size or even merged together (a situation not shown in FIG. 1A) by performing one or more epitaxial growth processes to grow additional semiconductor material on the fins in the source/drain regions of the device 10. The gate structures 16 for such FinFET devices may be manufactured using so-called “gate-first” or “replacement gate” (gate-last) manufacturing techniques.
One problem that is encountered in forming FinFET devices relates to preventing leakage currents underneath the fins 14, which are referred to as so-called “punch through” leakage currents. One prior art effort to eliminate or reduce such undesirable punch through leakage currents was performing an ion implantation process to form counter-doped punch through stop regions 22 that were positioned at approximately the intersection between the fin 14 and the remaining portion of the substrate 12. For an N-type device 10, the punch through stop regions 22 were created by implanting a P-type dopant, and for a P-type device 10 the punch through stop regions 22 were created by implanting an N-type dopant. The implant process that is performed to create the punch through stop regions 22 was typically performed shortly after formation of the fins 14 and prior to formation of the gate structure. However, obtaining an accurately doped punch through stop region 22 that is properly positioned underneath the active fin 14 is very difficult to accomplish, especially given that the additional thermal heating processes that are involved in subsequent process steps will further drive dopant diffusion and make it harder to control the location of the punch through stop regions 22. If the dopant from the counter-doped punch through stop regions 22 diffuses into the fins 14 during subsequent annealing processes, it would cause threshold voltage fluctuation because of the random amount of the counter-dopant diffused into fins 14 of different devices, which would severely compromise the circuit performance. Moreover, performing such ion implantation processes to form the punch through stop regions 22 can result in the formation of undesirable stacking faults in the upper portion of the fin 14, i.e., the region of the fin that will be surrounded by the gate structure 16 and serve as the channel region for the device 10. The presence of such stacking faults within the fin 14 may result in reduced device performance.
In some cases, efforts have been made to form such counter-doped regions 22 by depositing doped layers of silicon dioxide or forming doped spacers made of silicon dioxide adjacent the fins 14 and thereafter performing a heating process to cause the dopants in the layer of material or the spacer to migrate into the fins 14 at the desired location. One problem with this approach is that, in some cases, after formation of the layer of material or the spacers, the empty spaces between the fins 14 was typically filled with a flowable oxide material due to the better gap fill capabilities of the flowable oxide material as compared to deposited oxide materials, i.e., oxide material formed by, for example, plasma enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. Such flowable oxide material is typically formed by depositing a liquid-like state SiOx material and performing one or more heating processes to cure and densify the material to SiO2. Unfortunately, the flowable oxide material tends to etch at a faster rate than does the deposited oxide materials that were used to form the doped layers of silicon dioxide or the doped silicon dioxide spacers. Using this prior art approach, when it came time to recess the various insulating materials so as to “reveal” the portion of the fin that will serve as the channel region for the device, it was difficult to accurately control the height of the revealed fin due to the difference in etch rate between the flowable oxide material and the deposited oxide materials. Such variations in fin height can lead to a reduction in device performance or inconsistency in the performance of integrated circuits incorporating such devices.
The present disclosure is directed to various novel methods of forming punch through stop regions on FinFET devices on CMOS-based IC products using doped spacers that may solve or reduce one or more of the problems identified above.